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september 2009 doc id 15104 rev 1 1/40 AN2839 application note l6228 fully-integrated two- phase stepper motor driver introduction modern motion control applicati ons need more flexibility, whic h can only be addressed with specialized ic products. the l6228 is a fully-in tegrated stepper motor driver ic specifically developed to drive a wide range of two-phase (bipolar) stepper motors. this ic is a one- chip, cost-effective solution that includes several unique circuit design features. these features, including a decoding logic that can generate three different stepping sequences, allow the device to be used in many applicati ons, including microstepping. the principal aim of this development project was to produce an easy-to-use, fully-protected power ic. in addition, several key functions, such as pr otection circuitry and pwm current control, drastically reduce the number of external components to meet requirements for many different applications. the l6228 is a highly-integrated, mixed-signal power ic that allows the user to easily design a complete motor control system for two-phase bipolar stepper motors. figure 1 shows the l6228 block diagram. the ic integrates eight power dmos?s, a centralized logic circuit that implements the phase generation and a constant t off pwm current co ntrol technique (quasi-synchronous mode) for each of the two phases of the motor, plus other added features for safe operation and flexibility. figure 1. l6228 block diagram !-v *$7( /2*,& 67(33,1* 6(48(1&( *(1(5$7,21 29(5 &855(17 '(7(&7,21 29(5 &855(17 '(7(&7,21 *$7( /2*,& 9 &3 9 %227 (1 &21752/ &:&&: *1' *1' *1' *1' 95() $ 9 %227 9 9 9 6$ 9 6% 287 $ 287 $ 287 % 287 % 6(16( $ &+$5*( 3803 92/7$*( 5(*8/$725 21(6+27 021267$%/( 0$6.,1* 7,0( 7+(50$/ 3527(&7,21 9 %227 9 %227 2&' % 2&' $ 9 9 %5,'*($ 6(16( &203$5$725 %5,'*(% 5& $ 6(16( % 95() % 5& % +$/))8// &/2&. 5(6(7 / 3:0 www.st.com
contents AN2839 2/40 doc id 15104 rev 1 contents 1 designing an applicat ion with l6228 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 current ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 voltage ratings and operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 choosing the bulk capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 sensing resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 external components for the charge pump . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 sharing the charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8 reference voltage for pwm current control . . . . . . . . . . . . . . . . . . . . . . . 12 1.9 input logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.10 en pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.11 programmable off time monostable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.11.1 off time selection and minimum on time . . . . . . . . . . . . . . . . . . . . . . . . 16 1.11.2 decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.12 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.13 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.13.1 maximum output current versus selectable devices . . . . . . . . . . . . . . . 23 1.13.2 power dissipation and thermal analysis with practispin tm software . . 23 1.14 choosing the decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.15 choosing the stepping sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.16 microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 appendix a demonstration boa rd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 a.1 practispin tm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 a.2 l6228n evaluation with eval6208n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 a.2.1 important notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 a.3 eval6228qr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AN2839 list of figures doc id 15104 rev 1 3/40 list of figures figure 1. l6228 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. supply voltage of high-side gate drivers versus supply voltage . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. currents and voltages during the dead time at the beginning of the off time . . . . . . . . . . . . 5 figure 4. voltage at the two outputs at the beginning of the off-time. . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. typical application and layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. two situations that must be avoided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. sharing the charge-pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. obtaining a variable voltage through a pwm output of a c . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. logic input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. en input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. simplified schematic of the pwm current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13. output current regulation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 14. typical off time vs. c off for several values of r off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 15. minimum on time vs. c off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16. fast decay mode output stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. slow decay mode output stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. pwm controller loses the current regulation due to minimum on time . . . . . . . . . . . . . . . . 18 figure 19. pwm controller loses the current regulation due to minimum on time - detail . . . . . . . . . . 18 figure 20. simplified circuitry of the overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 21. overcurrent operation: timing 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 22. overcurrent operation: timing 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 23. typical disable time vs. c en for several values of r en . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 24. typical delay time vs. c en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 25. ic dissipated power versus output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 26. maximum output current vs. selectable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 27. power dissipation and thermal analysis with practispin tm software . . . . . . . . . . . . . . . . . 24 figure 28. torque instability in full-step mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 29. balanced half step for low torque ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 30. realizing half-step current shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 31. microstepping application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 32. microstepping reference voltages, output currents and clock signal . . . . . . . . . . . . . . 27 figure 33. using fast decay during a high, negative current slope . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 34. application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 35. practispin tm pc software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 36. practispin tm st7 demonstration board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 37. eval6208n electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 38. eval6228qr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 39. eval6228qr comp onent placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 40. eval6228qr top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 41. eval6228qr bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 42. eval6228qr electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
designing an application with l6228 AN2839 4/40 doc id 15104 rev 1 1 designing an application with l6228 1.1 current ratings with mosfet (dmos) devices, unlike bipolar transistors, the current under short-circuit conditions is, at a first appr oximation, limited by the r ds(on) of the dmos themselves and can reach very high values. the l6228?s out pins and the two v sa and v sb pins are rated for a maximum of 1.4 arms and 2.8 a peak (typical values), corresponding to a total of 2.8 arms (5.6 a peak) for the whole ic. these values are meant to avoid damaging the metal structures, including the metalliz ation on the die and bond wires . in practical applications, however, the maximum-allowable current is less than these values, due to power dissipation limits (see section 1.13 ). the device has a built-in overcurrent detection (ocd) that provides protection against short-circuits between the outputs and between an output and ground (see section 1.12 ). 1.2 voltage ratings and operating range the l6228 requires a single supply voltage (v s ) for the motor supply. internal voltage regulators provide the 5 and 10 volts required for the internal circuitry. the operating range for v s is 8 to 52 v. to prevent the device from operating at an insufficient supply voltage, an undervoltage lockout (uvlo) circuit shuts down the device when the supply voltage falls below 5.5 v; to resume normal operating conditions, v s must then exceed 6.3 v. the hysteresis is provided to avoid false intervention of the uvlo function during fast v s ringings. it should be noted, however, that the dmos' r ds(on) is a function of the v s supply voltage. in fact, when v s is less than 10 v, r ds(on) is adversely affected, and this is particularly true for the high-side dmos?s that are driven from the v boot supply. this supply is obtained through a charge pum p from the internal 10 v supp ly, which will tend to reduce its output voltage when v s goes below 10 v. figure 2 shows the supply voltage of the high- side gate drivers (v boot - v s ) versus the supply voltage (v s ). figure 2. supply voltage of high-side gate drivers versus supply voltage note that v s must be connected to both v sa and v sb since the bootstrap voltage (at the v boot pin) is the same for the two h-bridges. the integrated dmos?s have a rated drain- source breakdown voltage of 60 v. however, v s should be kept below 52 v, since in normal working conditions the dmos?s see a v ds voltage that will exceed the v s supply. in particular, when using the fast-decay mode, at the beginning of the off time (when all the dmos?s are off during dead time) the sense pin sees a negative spike due to a non- negligible parasitic inductance of the pcb path from the pin to gnd. !-v
AN2839 designing an application with l6228 doc id 15104 rev 1 5/40 this spike is followed by a stable negative voltage due to the drop on r sense . one of the two out pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it (see figure 3 ). the typical duration of this spike is 30 ns. at the same time, the other out pin of the same bridge sees a voltage above v s , due to the pcb inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. it turns out that, in fast decay mode, the highest differential voltage is observed between the two out pins of the same bridge, at the beginning of the off time, and this must always be kept below 60 v (a) . the same high- voltage condition exists when a step is made and the direction of the current flow reverses in the bridge. figure 3. currents and voltages during the dead time at the beginning of the off time figure 4 on page 6 shows the voltage waveforms at the two out pins referring to a possible practical situation, with a peak output current of 1.4 a, v s = 52 v, r sense = 0.33 , t j = 25 c (approximately) and a good pcb layout. the below-ground spike amplitude is -2.65 v for one output; the other out pin is at about 57 v. in these conditions, the total differential voltage reaches almost 60 v, which is the absolute maximum rating for the dmos. it is extremely important to keep the differential voltage between two output pins belonging to the same full bridge within rated values. this can be accomplished by correctly selecting the value of the bulk capacitor and equivalent series resistance (esr), according to the current peaks and chopping style, and by adopting good layout practices to minimize pcb parasitic inductances (a) . a. refer to [ 3 ] in references . !-v 9 6 6(16( 287 287 5 6(16( , 5 6(16( ,9 )'lrgh 3&%3dudvlwlf ,qgxfwdqfh 3&%3dudvlwlf ,qgxfwdqfh %xon&dsdflwr u (txlydohqw&lufxlw (65 (6/ 5 6(16( 9 6 9 )'lrgh 'dqjhurxv +ljk'liihuhqwldo9rowdjh
designing an application with l6228 AN2839 6/40 doc id 15104 rev 1 figure 4. voltage at the two outputs at the beginning of the off-time 1.3 choosing the bulk capacitor since the bulk capacitor, placed between the v s and gnd pins, is charged and discharged during ic operation, its ac current capability must be greater than the rms value of the charge/discharge cu rrent. this current flows from the capacitor to the ic during the on time (t on ) and from the ic (in fast decay; from the power supply in slow decay) to the capacitor during the off time (t off ). the rms value of the current flowing into the bulk capacitor depends on the peak output current, output current ripple, switching frequency, duty cycle and chopping style. it also depends on the characteristics of the power supply. a power supply with poor high-frequency performances (or long, inductiv e connections to the ic) will cause the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; rms current in the capacitor, however, does not exceed the rms output current. the bulk capacitor value (c) and the esr determine the amount of voltage ripple on the capacitor itself and on the ic. in slow decay, neglecting the dead-time and output current ripple, and assuming that during the on time the capacitor is not recharged by the power supply, the voltage at the end of the on time is: equation 1 so the supply voltage ripple is: equation 2 where i out is the output current. in fast decay, instead, the recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. this can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52 v). in fast decay the supply voltage ripple is about: !-v 2xw 2xw v s i out ? esr t on c ---------- - + ?? ?? ? i out esr t on c ---------- - + ?? ?? ?
AN2839 designing an application with l6228 doc id 15104 rev 1 7/40 equation 3 always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the dead-time. usually (if c > 100 f) the capacitance role is much less than the esr, in which case the supply voltage ripple can be estimated as: equation 4 equation 5 for example, if a maximum ripple of 500 mv is allowed and i out = 1 a, the capacitor esr should be lower than: equation 6 equation 7 in fact, current sunk by the v sa and v sb pins of the device is subject to higher peaks due to the reverse recovery charge of the internal freewheeling diodes. the duration of these peaks is very short and can be filtered using a small value (100200 nf), good-quality ceramic capacitor connected as close as possible to the v sa , v sb and gnd pins of the ic. the bulk capacitor should be chosen with a maximum operating voltage 25% greater than the maximum supply voltage, considering also the power supply tolerances. for example, with a 48 v nominal power supply with 5% tole rance, the maximum voltage will be 50.4 v, and the operating voltage for the capacitor should be at least 63 v. 1.4 layout considerations working with devices that combine high-power switches and control logic in the same ic, special attention has to be paid to the layout of the pcb. in extreme cases, power dmos commutation can induce noise that may cause improper operation in the logic section of the device. noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through gnd or supply connections. logic connection s, especially high-impedance nodes (actually all logic inputs, see section 1.9 ), must be kept far from switching nodes and paths. with the l6228 in particular, the external components for the charge-pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at a re latively high frequency (600 khz) . the primary means of minimizing conducted noise is to work on a good gnd layout (see figure 5 on page 8 ). i out 2esr ? t on t off + c -------------------------------- + ?? ?? ? i out esr ? 2i out esr ?? esr 0.5v 1a ------------ < 500m = in slow decay in fast decay esr 1 2 -- - 0.5v 1a ------------ ? < 250m =
designing an application with l6228 AN2839 8/40 doc id 15104 rev 1 figure 5. typical application and layout suggestions the high current gnd tracks (the tracks connected to the sensing resistors) must be connected directly to the negative terminal of the bulk capacitor. a good quality, high- frequency bypass capacitor is also required (typically a 100200 nf ceramic would suffice), since electrolytic capacitors show a poor high-f requency performance. both bulk electrolytic and high-frequency bypass capacitors have to be connected with short tracks to v sa , v sb and gnd. on the l6228 the gnd pins are the logic gnd since only the quiescent current flows through them. the logic gnd and power gnd should be connected together in a single point , the bulk capacitor, to keep noise in the power gnd from affecting the logic gnd. specific care should be paid layouting the path from the sense pins through the sensing resistors to the negative terminal of the bulk capacitor (power ground). these tracks must be as short as possible to minimize parasitic inductances that can cause dangerous voltage spikes on the sense and out pins (see section 1.2 ); for the same reason the capacitors on v sa , v sb and gnd should be very close to the gnd and supply pins. refer to section 1.5 for information on selecting the sense resistors. the traces connected to v sa , v sb , sense a , sense b , and the four out pins must be designed with adequate width, since high currents flow through these traces, and layer changes should be avoided. should a layer change prove necessary, multiple and large via holes have to be used. a wide gnd copper area can be used to improve heat removal, thus reducing thermal resistance. figure 6 on page 9 shows two typical situations that must be avoided. an important consideration regarding the location of the bulk capacito rs is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. the diode shown in figure 6 prevents the recirculation current from reaching the capacitors and will result in a high voltage on the ic pins that can damage the device. having a switch or a power connection that can disconnect the capacitors from the ic, while there is still current in the motor, will also result in a high volt age transient since there is no capacitance to sink th e recirculating current. !-v 9 6 9 9 uhi 9 (1 &/2& . +$/))8// 5(6(7 &21752/ &:&&: 9 uhi$ 9 uhi% 5& $ 5& % *1' *1' *1' *1' 6(16( $ 6(16( % 9 6$ 9 6% 9 %22 7 &3 287 % 287 % 287 $ 287 $ ' ' 5 5 5 5 5 5 & & & & & & & & / ?& ru &xvwrp/rjlf 3kdvh 6whsshu0rwru /rjlf6xsso\ 9
AN2839 designing an application with l6228 doc id 15104 rev 1 9/40 figure 6. two situations that must be avoided 1.5 sensing resistors each motor winding current flows through the corresponding sensing resistor, causing a voltage drop that is used, by the logic, to control the peak value of the load current. two important points must be taken into account when choosing the r sense value. the sensing resistor dissipates energy and provides dangerous negative voltages on the sense pin during the current recirculation. for this reason, the resistance of this component should be kept low. the voltage drop across r sense is compared with the reference voltage (on the v ref pin) by the internal comparator. the lower the r sense value, the higher the peak current error due to noise on the v ref pin and to the input offset of the current sense comparator: r sense values that are too small must be avoided. a good compromise is to calculate the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (i peak ), is about 0.5 v: r sense = 0.5 v/i peak . the sensing resistor must be of a non-inductive type in order to avoid dangerous negative spikes on the sense pins. wire-wound resistors cannot be used here, while metallic film resistors are recommended for th eir high peak curr ent capability and low inductance. for the same reason, the connections bet ween the sense pins, c6, c7, v sa , v sb and gnd pins (see figure 5 on page 8 ) must be as short as possible (also see section 1.4 ). the average power dissipated by the sensing resistor is: fast decay recirculation: p r i rms 2 r sense slow decay recirculation: p r i rms 2 r sense d where d is the duty-cycle of the pwm current control and i rms is the rms value of the load current. nevertheless, the peak value of the dissipated power should be taken into account when choosing the power rating of the sensing resistor. equation 8 !-v $/.{tconnectthelogic'.$here 6oltagedropduetocurrentinsense pathcandisturblogic'.$ $/.{4putadiodehere 2ecirculatingcurrentcannotflowintothe bulkcapacitorandcausesahighvoltage spikethatcandamagethe)# *1 ' *1 ' *1 ' *1 ' 6( 16( $ 6( 16( % 9 6$ 9 6% 5 & & , 9 6 9 p r i pk 2 r sense ?
designing an application with l6228 AN2839 10/40 doc id 15104 rev 1 where i pk is the peak value of the load current. using multiple resistors in para llel will help obtain the required power rating with standard resistors and reduce the inductance. the r sense tolerance reflects on the peak current error: 1% resistors should be preferred. ta bl e 1 shows the recommended values for r sense (to obtain a 0.5-v drop) and power ratings for typical examples of current peak values. 1.6 external components for the charge pump an internal oscillator, with its output at the cp pin, switches from gnd to 10 v with a typical frequency of 600 khz ( figure 7 ). figure 7. charge pump when the oscillator outp ut is at ground, c 5 is charged by v s through d 2 . when it rises to 10 v, d 2 is reverse-biased and the charge flows from c 5 to c 8 through d 1 , so the v boot pin, after a few cycles, reaches the maximum voltage of v s + 10 v - v d1 - v d2 , which supplies the high-side gate drivers. with a differential voltage between v s and v boot of about 9 v and both bridges switching at 50 khz, the typical current drawn by the v boot pin is 1.85 ma. table 1. r sense recommended values i pk r sense value [ ] r sense power rating [w] alternatives 0.25 2 0.125 0.5 1 0.25 1 0.5 0.5 2 x 1 , 0.25 w paralleled !-v , 9 6 99 ' 9 6 9 ' i n+] 9 6$ 9 6% 9 % 227 &3 ' ' & & 5 '6 21 9 9 9 5 '6 21 rkp rkp 7r +l jk6lgh *d w h ' u l y h u v 9 i n+] &kd u j h 3x p s 2vfloodwru 9 6 99 ' 9 '
AN2839 designing an application with l6228 doc id 15104 rev 1 11/40 to minimize interferences with the rest of the circuit, care must be taken in realizing the pcb layout of the c5, d1 and d2 connections (also see section 1.4 ). the recommended values for the charge pump circuitry are: d1, d2: 1n4148 c5: 10 nf, 100 v ceramic c8: 20 nf, 25 v ceramic due to the high charge-pump frequency, fast diodes are required. when connecting the cold side of the bulk capacitor (c8) to v s instead of gnd, the average current in the external diodes during operation is less than 10 ma; at startup (when v s is provided to the ic) it is less than 200 ma while the reverse voltage is about 10 v in all conditions. in4148 diodes withstand about 200 ma of dc current (1 a peak), and the maximum reverse voltage is 75 v, so they should fit for the majority of applications. 1.7 sharing the charge pump circuitry if more than one device is used in the application, the charge pump from one l6228 can be used to supply the v boot pins of several ics. the unused cp pins on the slaved devices are left unconnected, as shown in figure 8 . a 100 nf capacitor (c8) should be connected to the v boot pin of each device. the supply voltage pins v s of the devices sharing the charge pump must be connected together. the higher the number of devices sharing the same charge pump, the lower the differential voltage available for the gate drive (v boot - v s ), causing a higher r ds(on) for the high-side dmos, and as such a higher dissipating power. better performance can also be obtained using a 33 nf capacitor for c5 and schottky diodes (bat47 are recommended). having more than three or four devices sharing the same charge-pump circuitry is not recommended since this will reduce the v boot voltage and increase the high-side mosfet?s on-resistance, and therefore the power dissipation. figure 8. sharing the charge-pump circuitry !-v 9 6$ 9 6% 9 %22 7 &3 ' %$7 ' %$7 & q) & q ) 7r+ljk6lgh *dwh'ulyhuv 9 6$ 9 6% 9 %2 2 7 & q) 7r+ljk6lgh *dwh'ulyhuv 7rrwkhughylf hv &3 / /
designing an application with l6228 AN2839 12/40 doc id 15104 rev 1 1.8 reference voltage for pwm current control the device has two analog inputs, v refa and v refb , connected to the internal sense comparators, to control the peak value of the motor current through the integrated pwm circuitry. in typical applications, these pins are connected together to obtain the same current in the two motor windings (one exception is the microstepping operation; see section 1.16 ). a fixed reference voltage can be easily obtained through a resistive divider from an available 5 v voltage rail (maybe the one supplying the c or the rest of the application) and gnd. a very simple way to obtain a variable voltage without using a dac is to low-pass filter a pwm output of a c (see figure 9 ). assuming that the pwm output swings from 0 to 5 v, the resulting voltage will be: equation 9 where d c is the duty-cycle of the pwm output of the c. assuming that the output impedance of the c is lower than 1 k , with r lp = 56 k , r div = 15 k , c lp = 10 nf and a c pwm switching from 0 to 5 v at 100 khz, the low-pass filter?s time constant is about 0.12 ms and the remaining ripple on the v ref voltage will be about 20 mv. using higher values for r lp , r div and c lp will reduce the ripple, but the reference voltage will take more time to vary after changing t he duty-cycle of the c pwm, and too-high values of r lp will also increase the impedance of the v ref net at low frequencies, causing a poor noise immunity. as sensing resistor values are typically kept small, a small noise on the v ref input pins might cause a considerable error in the output current. it is recommended to decouple these pins with ceramic capacitors of some tens of nf, placed very close to the v ref and gnd pins. note that the v ref pins cannot be left unconnected, while, if connected to gnd, zero current is not guaranteed due to voltage offset in the sense comparator. the best way to cut down the ic?s power consumption and cl ear the load current is by pullin g down the en pin. in slow decay, with a very small reference voltage, the pwm?s integrated circuitry can lose control of the current due to the minimum-allowed duration of t on (see section 1.11 ). figure 9. obtaining a variable voltage through a pwm output of a c v ref 5v d c r div ?? r lp r div + -------------------------------------------- - = !-v 5 /3 & /3 9 uhi *1' 3:02xwsxw rid ?& 5 ',9
AN2839 designing an application with l6228 doc id 15104 rev 1 13/40 1.9 input logic pins cw/ccw, control, reset, half/full, cloc k are cmos/ttl-compatible logic input pins. the input comparator has been realized with hysteresis to ensure the required noise immunity is met. typical values for turn-on and turn-off thresholds are v th,on = 1.8 v and v th,off = 1.3 v. as shown in figure 10 , these pins are esd-protected (2 kv human-body electro-static discharge), and can be directly co nnected to the logic outputs of a c; a series resistor is generally not recommended as it could cause inducted noise and disturb the inputs. all logic pins enforce a specific behavior and cannot be left unconnected. figure 10. logic input pins 1.10 en pin the en pin is bi-directional: as an input, with a comparator similar to the other logic input pins (ttl/cmos with hysteresis), it controls the state of the power dmos. when this pin is at a low logic level, all the power dmos?s are turned off. the en pin is also connected to the open-drain output of th e protection circuit that will pull the pin to gnd if overcurrent or over- temperature conditions exist. for this reason, the en pin must be driven through a series resistor of 2.2 kw minimum (for 5 v logic), to allow the voltage at the pin to be pulled below the turn-off threshold. a capacitor (c1 in figure 5 on page 8 ) connected between the en pin and gnd is also recommended to reduce the rms value of the output current when overcurrent conditions persist (see section 1.12 ). the en pin must not be left unconnected. figure 11. en input pin !-v 9 &21752/ +$/ ))8//&/2&. 5(6(7&:&&: (6' 3urwhfwlrq !-v 9 (1 (6' 3ur whfwlrq
designing an application with l6228 AN2839 14/40 doc id 15104 rev 1 1.11 programmable off time monostable the l6228 includes a constant off time pwm current controller for each of the two bridges. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power mosfet transistors and ground, as shown in figure 12 . as the current in the motor builds up, the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor becomes greater than the voltage at the reference input (v ref a or v ref b ), the sense comparator triggers the monostable, switching the bridge off. the power mosfets remain off for the time set by the monostable, and the motor current recirculates as defined by the selected decay mode, described in the next section. when the monostable times out, the brid ge will again turn on. since the internal dead time used to prevent cross- conduction in the bridge delays the turn-on of the power mosfets, the effective off time is the sum of the monostable time plus the dead time. figure 12. simplified schematic of the pwm current controller figure 13 on page 15 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the rc pin voltage and the status of the bridge. more details regarding the synchronous rectification and the output stage configuration are included in the next section. immediately after the power mosfet turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. the l6228 provides a 1 s blanking time, t blank , that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable. !-v '5,9(56 '($' 7,0( 6 4 5 '5,9(56 '($' 7,0( + + / / 287 $ru% 6(16( $ru% 5 6(16( 5& $ru% 5 2)) & 2)) 95() $ru% , 287 287 $ru% m v p$ %/$1.(5 6(16( &20 3$5$725 &20 3$ 5 $72 5 287387 02126 7$%/( 6(7 9 9 )5207+( /2:6,'( *$7('5,9(56 3+$6( 67(33(5027 25 %/$1.,1* 7,0( 02126 7$%/( 96 $ ru % 72*$7(/2*,&
AN2839 designing an application with l6228 doc id 15104 rev 1 15/40 figure 13. output current regulation waveforms figure 14 on page 16 shows the magnitude of the off time t off versus the c off and r off values. it can be approximately calculated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally- generated dead time with: 20 k r off 100 k 0.47nf c off 100 nf t dt = 1 s (typical value) therefore: t off(min) = 6.6 s t off(max) = 6 ms these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin?s rc a (or rc b ). the rise time t rcrise will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. therefore, the on time t on , which depends on the motors and supply parameters, has to be longer than t rcrise to allow the pwm stage to correctly regulate the current. furthermore, the on time t on cannot be shorter than the minimum on time t on(min) . !-v 2egulationwaveforms 2)) %& ' '$ w 21 w 2)) w 2)) %& 21 9 )dvw'hfd\ )dvw'hfd\ 6orz'hfd\ 6orz'hfd\ m vw %/$1. w 5&5,6( m vw '7 m vw '7 w 5&5,6( w 5&)$// w 5&)$// 6<1&+ 5212862548$6, 6<1&+5212865(&7,),&$7,21 m vw %/$1. 9 9 5& 9 6(16( 9 5() , 287 9 5() 5 6(16(
designing an application with l6228 AN2839 16/40 doc id 15104 rev 1 equation 10 equation 11 1.11.1 off time selection and minimum on time figure 15 shows the lower limit for the on time t on in order to obtain a good pwm current regulation capacity. it has to be said that t on is always longer than t on(min) because the device imposes this condition, but it can be shorter than t rcrise - t dt . in this last case, the device continues to work but the off time t off is not more constant. therefore, a small c off value gives more flexibility for th e applications (allows a shorter on time and, therefore, a higher switching frequency), but the smaller the value for c off , the more influential the noises on the circuit performance will be. 1.11.2 decay modes the control input is used to select the behavior of the bridge during the off time. when the control pin is low, the fast decay mode is selected and both transistors in the bridge are switched off during the off time. when the control pin is high, the slow decay mode is selected and only the low-side transistor of the bridge is switched off during the off time. figure 16 on page 17 shows the operation of the bridge in fast decay mode. at the start of the off time, both power mosfets are switched off and the current recirculates through the two opposite freewheeling diodes. the current decays with a high di/dt since the voltage across the coil is essentially the power supply vo ltage. after the dead time, the lower power mosfet in parallel with the conducting diode is turned on in synchronous rectification mode. in applications where the motor current is low, it is possible that the current decays completely to zero during the off time. at this point, if both power mosfets were operating in the synchronous rectification mode, it would be possible for the current to build in the opposite direction. to prevent this, only the lower power mosfet is operated in synchronous rectification mode. this operation is called quasi synchronous rectification . when the monostable times out, the t on t on min () >1.5 s (typ. value) = t on t rcrise t dt ? > ? ? ? t rcrise 600 c off ? = figure 14. typical off time vs. c off for several values of r off figure 15. minimum on time vs. c off am01697v1 1 10 100 1 . 10 3 1 . 10 4 cof f [ nf] to f f [ us ] r = 20 k r = 47 k r = 100 k 0.1 1 10 100 am0169 8 v1 1 10 100 coff [nf] to n ( m in ) [ us ] 0.1 1 10 100
AN2839 designing an application with l6228 doc id 15104 rev 1 17/40 power mosfets are turned on again after some delay set by the dead time to prevent cross-conduction. figure 17 shows the operation of the bridge in slow decay mode. at the start of the off time, the lower power mosfet is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slowly. after the dead time, the upper power mosfet is operated in the synchronous rectification mode. when the monostable times out, the lower power mosfet is turned on again after some delay set by the dead time to prevent cross-conduction. figure 16. fast decay mode output stage configurations figure 17. slow decay mode output stage configurations in some conditions (short off time, very low regulated current, high motor winding l/r) the system may need an on time shorter than 1.5 s. in such a case, the pwm current controller can lose the regulation. figure 18 and figure 19 on page 18 show the operation of the circuit in this condition. when the current first reaches the threshold, the bridge is turned off for a fixed time and the current decays. during the following on time, the current increases above the threshold, but the bridge cannot be turned off until the minimum 1.5 s on time has expired. since the current incr eases more during each on time than it decays during the off time, it keeps growing during each cycle, with a steady-state asymptotic value set by the duty cycle and load dc resistance. !-v " % - ) 4 . / ! ?s$%!$4)-% # 39.#(2/./53 2%#4)&)# !4)/. $ ? s3,/7$%!$ !-v % ( 0 , 7 1 2 $ m v'($'7,0( &6<1&+521286 5(&7,),& $7,21 ' m v'($'7,0(
designing an application with l6228 AN2839 18/40 doc id 15104 rev 1 the resulting peak current will be: equation 12 where d = t on / (t on + t off ) is the duty cycle and r load is the load dc resistance. 1.12 overcurrent protection to implement an overcurrent protection, a dedicated overcurrent detection (ocd) circuitry (see figure 20 on page 19 for a simplified schematic) senses the current in each high side. the power dmos?s are actually made up of thousands of individual identical cells, each carrying a fraction of the total current flowing. the current sensing element, connected in parallel to the power dmos, is made with only a few such cells, having a 1:n ratio compared to the power dmos. the total drain current is split between the output and the sense element according to the cell ratio. the sensed current is, then, a small fraction of the output current and will not contribute si gnificantly to power dissipation. i pk v s d r load ----------------- - ? = figure 18. pwm controller loses the current regulation due to minimum on time figure 19. pwm controller loses the current regulation due to minimum on time - detail am01701v1 am01702v1
AN2839 designing an application with l6228 doc id 15104 rev 1 19/40 figure 20. simplified circuitry of the overcurrent detection this sensed current is compared to an internally-generated reference to detect an overcurrent condition. an internal open-drain mosfet turns on when the sum of the currents in the bridges 1a and 2a or 1b and 2b reaches the threshold (2.8 a typical value); the open drain is internally-connected to the en pin. to ensure an overcurrent protection, this pin should be connected to an external rc network ( figure 20 ). figure 21 and figure 22 on page 20 show the device operating in an overcurrent condition (short to ground). when an overcurrent is detected, the internal open-drain mosfet pulls the en pin to gnd, switching off all 8 power dmos?s of the device and allowing the current to decay. if an overcurrent conditions persists, like a short to ground or a short between two output pins, the external rc network on the en pin (see figure 20 ) reduces the rms value of the output current by imposing a fixed disable time after each overcurrent occurrence. the values of r en and c en are selected to ensure proper operation of the device during a short-circuit condition. when the current flowing through the high-side dmos reaches the ocd threshold (2.8 a typ.), after an internal propagation delay (t ocd(on) ) the open drain starts discharging c en . when the en pin voltage falls below the turn-off threshold (v th(off) ), all the power dmos?s turn off after the internal propagation delay (t d(off)en ). the current begins to decay as it circulates through the freewheeling diodes. since the dmos?s are off, there is no current flowing through them and no current to sense; therefore, the ocd circuit, after a short delay (t ocd(off) ), switches the internal open-drain device off, and r en can charge c en . when the voltage at the en pin reaches the turn-on threshold (v th(on) ), after the t d(on)en delay, the dmos?s turn on and the current restarts. even if the maximum output current can be very high, the external rc network provides a disable time (t disable ) to ensure a safe rms value (see figure 22 ). !-v 29(57(03(5$785( , 5() , $ , $ q , $ q 32:(56(16( fhoo 32:(56(16( fhoo 32:(5'026 qfhoov 32:(5'026 qfhoov +,*+6,'('026v2) 7+(%5,'*($ 287 $ 287 $ 9 6$ , $ , $ , $ q )5207+( %5,'*(% 2&' &203$5$725 2&' &203$5$725 72*$7( /2*,& ,17(51$/ 23(1'5$,1 5 '621 7 7<3 & (1 5 (1 (1 9 m &ru/2*,&
designing an application with l6228 AN2839 20/40 doc id 15104 rev 1 the maximum value reached by the current depends on its slew rate, and thus on the state of the short-circuit, the supply voltage, and on the total intervention delay (t delay ). one can see that after the first current peak, the maximum value reached by the output current decreases; this is because the capacitor on the en pin is discharged starting from a lower voltage, resulting in a shorter t delay . the following approximate relations estimate the disable time and the first ocd intervention delay after the short-circuit (worst case). the time the device remains disabled is: equation 13 where: equation 14 v en(low) is the minimum voltage reached by the en pin and can be estimated by the relation: equation 15 the total intervention time is: equation 16 figure 21. overcurrent operation: timing 1 figure 22. overcurrent operation: timing 2 !-v !-v t disable t ocd off () t en rise () t don () en ++ = t en rise () r en c en v dd v en low () ? v dd v th on () ? --------------------------------------------------- - ln ?? = v en low () v th off () e t doff () en t ocd off () + r opdr c en ? -------------------------------------------------------------------------- ? = t delay t ocd on () t en fall () t doff () en ++ =
AN2839 designing an application with l6228 doc id 15104 rev 1 21/40 where: equation 17 t ocd(off) , t ocd(on) , t d(on)en , t d(off)en and r opdr are device-intrinsic parameters and v dd is the pull-up voltage applied to r en . the external rc network, c en in particular, must be selected to obtain a reasonable fast ocd intervention (short t delay ) and a safe disable time (long t disable ). figure 23 and figure 24 show both t disable and t delay as a function of c en : at least 100 s for t disable are recommended, keeping the delay time between 1 and 2 s at the same time. the internal open drain can also be turned on if the device experiences an over-temperature (ovt) condition. the ovt will cause the device to shut down when the die temperature exceeds the ovt threshold (t j > 165 c typ.). since the ovt is also connected directly to the gate-drive circuit (see figure 1 on page 1 ), all the power dmos?s will shut down, even if the en pin voltage is still over v th(off) . when the junction temperature falls below the ovt turn-off threshold (150 c typ.), the open drain turns off, c en is recharged up to v th(on) and the power dmos?s are turned back on. 1.13 power management even when operating at current levels well below the maximum ratings of the device, the operating junction temperature must be kept below 125 c. figure 25 on page 22 shows the ic?s dissipated power versus the rms load current in four different driving sequences, assuming the supply voltage is 24 v. t en fall () r opdr c en v dd v th off () ------------------------------ ln ?? = figure 23. typical disable time vs. c en for several values of r en figure 24. typical delay time vs. c en am01706v1 0 0 1 0 1 1 1 10 100 1 . 10 3 c en [n f ] t di s able [ s ] r en = 220 k r en = 100 k r en = 47 k r en = 33 k r en = 10 k !-v t $%,!9 ;?s= # %. ;n & =
designing an application with l6228 AN2839 22/40 doc id 15104 rev 1 figure 25. ic dissipated power versus output current !-v
AN2839 designing an application with l6228 doc id 15104 rev 1 23/40 1.13.1 maximum output curre nt versus selectable devices figure 26 shows a performance comparison between the l6228 (standard power) and the l6208 (high power) for different packages, with the following assumptions. normal drive mode (two-phase on). supply voltage: 24 v; switching frequency: 30 khz. t amb = 25 c, t j = 125 c. maximum r ds(on) (taking into account the process spread) considered, at 125 c. maximum quiescent current i q (taking into account the process spread) considered. pcb is an fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m) for so and powerdip packages (d, n suffixes). pcb is an fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer for the powerso package (pd suffix). for each device (on the x axis), the y axis reports the maximum output current. figure 26. maximum output current vs. selectable devices 1.13.2 power dissipation and ther mal analysis with practispin tm software the practispin tm software includes a power dissipation and thermal analysis section that helps to calculate the ic power dissipation and estimate its junction temperature through a simulation. the purpose of this section is to help perform a quick evaluation of the device, package and dissipating copper area required by the user?s application, and is a good starting point when designing an application (from the power dissipation and thermal points of view). software results, especially thermal results, need to be confirmed on-bench. !-v / ' / 1 / 3 ' / ' / 1 / 3 ' ,oadcurrent ;!=
designing an application with l6228 AN2839 24/40 doc id 15104 rev 1 the input data for simulation is divided in three sections. application data: to select the motor charac teristics and its config uration, the driving parameters and the analysis type (stead y state, single pulse or repeated pulse analysis) device data: to choose the device part number and edit some available ic parameters. pcb data: to select the package, pcb dissipating characteristics and ambient temperature the output data includes the temperature and current profile waveforms, the estimated ic power dissipation and junction temperature. for more details on the formulas used in the software, refer to the "help" menu of the power dissipation and thermal analysis window. figure 27. power dissipation and thermal analysis with practispin tm software 1.14 choosing the decay mode the l6228 can operate in either fast or slow decay mode, each having a specific recirculation path for the current during off time. in slow decay mode, only the lower dmos is turned off and the current recirculates around the upper half of the bridge so that the voltage across the coil is close to zero. in fast decay mode, both dmos?s are turned off and the current recirculates back to the power supply rail so that the voltage across the coil is essentially the power supply voltage itself. slow decay operation provides several advantages: for a given peak current and off time, the current ripple is minimized. the same is true for acoustic noise and losses in the motor iron (achieving the same current ripple with fast decay mode would require a shorter off time resulting in a higher switching frequency and higher power dissipation in the ic). as current recirculates in the upper half of the bridge and both high-side dmos?s in the same bridge are on, synchronous rectification is realized, minimizing power dissipation in the power switches. furthermore, since no output pin goes below gnd (see section 1.2 ), no power is dissipated on the sense resistor during the off time (see section 1.5 ). am01710v1
AN2839 designing an application with l6228 doc id 15104 rev 1 25/40 on the other hand, slow decay can be undesirable in some situations, for example when current has to be regulated at very low values or the motor winding l/r ratio is high. in these cases, an on time shorter than the minimum t on (about 1.5 s) may be requested to regulate the current, and this can cause the pwm controller to lose the regulation (refer to section 1.11 ). another situation where fast decay should be preferred to slow decay is when the regulated current is expected to vary over time with a given profile (enforced, providing a variable voltage on the v ref pins - see section 1.16 ). here fast decay helps to track fast decreasing edges in the desired profile. 1.15 choosing the stepping sequence the device can provide three different sequences to run a stepper motor: full-step, two- phase on (normal drive), full-step, one-phase on (wave drive) and half-step. if half-step driving is used, the motor advances by half a step after each clock pulse, obtaining a higher position re solution and reducing instability du e to low torque regions in certain motors' speed-torque diagrams, when used in full-step mode. figure 28. torque instability in full-step mode. when this driving method is used, the torque is affected by ripple because in odd-numbered states, when both coils are driven, the total current in the motor windings is double that found in even-numbered states. a way to avoid the high torque ripple in half-step mode is to supply the motor with a higher current (by a factor of ) during the even-numbered states, in which only one winding is energized, simply by applying a higher reference voltage at the v refa , v refb pins during these states (see figure 29 on page 26 ) (b) . b. also refer to [ 2 ] in references . !-v 4o r q u e 3pee d 2 2
designing an application with l6228 AN2839 26/40 doc id 15104 rev 1 figure 29. balanced half step for low torque ripple a simple circuit to generate two different reference voltages is shown in figure 30 . r 1 and r 2 should be chosen to have: equation 18 and r 3 should be: equation 19 a similar circuit can also be used to modify the reference voltage in other situations. for example, it is possible at a constant rotation speed to reduce the motor torque and to increase it during acceleration and deceleration. a second transistor can be added to implement four different reference voltages, selectable by two logic signals. figure 30. realizing half-step current shaping normal and wave drive are full-step modes. in wave drive mode, the two motor windings are alternately energized, while in normal drive, both the windings are energized in each state, increasing the torque by a factor of . on the other hand, the total current in the motor is double, so the efficiency is similar. in wave drive mode, the torque ripple is higher than in normal drive mode. !-v #lock ) ! ) " 6 ref! 6 ref" 6 ref 9 ref ? "alancedhalfstep 3tartupor re set v ref high , v ref 2 ? 5v r 2 r 1 r 2 + --------------------- - ? == r 3 r 1 r 2 ? 21 ? () r 1 r 2 + () ? ---------------------------------------------------- - = am0171 3 v1 5v during odd numbered states 0v during even numbered states gnd +5v r 1 r 2 r 3 4.7k 15k to v ref pin(s) 2
AN2839 designing an application with l6228 doc id 15104 rev 1 27/40 1.16 microstepping microstepping operati on has several advantages, includi ng the absence of any instability phenomena due to low torque regions in certain motors' speed-torque diagrams (see figure 28 on page 25 ), reduction of mechanical noise and increased position resolution. the l6228 can be used as a two-phase microstepping driver ic (c) . the controller?s circuitry allows for an easy and inexpensive design with such a device. by controlling the v ref inputs, it is possible to obtain in the two phases variable output currents with a sine wave shape. a variable voltage proportional to the desired output current is applied to each reference pin. for microstepping, the two inputs are rectified sine-wave voltages with a phase delay of 90. the l6228 is operated in the normal drive mode and the frequency of the two sine wave voltages must be 1/4 of the clock frequency. figure 31 shows a circuit to generate the two sine wave signals using low-pass filters and two pwm outputs of a c (see section 1.8 ). figure 32 shows the v ref voltages, the clock signal and the output currents. figure 31. microstepping application figure 32. microstepping reference voltages, output currents and clock signal the slow decay mode can sometimes be inadequat e, particularly at high rotation speeds, since it does not allow the motor current to decay quickly enough and follow the decreasing c. refer to [ 5 ] in references . !-v !-v 6 ref! 6 ref" ) /54" ) /54! #,/#+ ) -!8
2 3%.3% 6 ) -!8
2 3%.3% 6 ) -!8 ) -!8 ) -!8 ) -!8 6 6 ?
designing an application with l6228 AN2839 28/40 doc id 15104 rev 1 slope of the desired sine wave. in cases like this, the fast decay mode can just be applied during the negative slope of the current ( figure 33 ). the disadvantage is an increased current ripple in the other winding (where the current is increasing and fast decay is not needed). figure 33. using fast decay duri ng a high, negative current slope am01716v1
AN2839 application example doc id 15104 rev 1 29/40 2 application example the first step is to select t he type of decay. for the purpose of this example, we will implement slow decay, which allows a lower power dissipation, lower ripple and avoids voltages below gnd at the output pins during recirculation. the power dissipation and thermal analysis practispin tm tool allow calculation of the ic power dissipation and estimation of the junction temperature. the purpose of this section is to help perform a fast evaluation of the device, package and dissipating copper area required by the user?s application, and is intended as a good starting point when designing an application (from the power dissipation and thermal points of view). software results, especially thermal results, need to be confirmed on-bench. the bulk capacitor needs to withstand at least 24 v + 5% + 25% ? 32 v. a 50 v capacitor will be used. allowing a voltage ripple of 200 mv, the capacitor?s esr should be lower than 200 mv/0.5 a = 400 m ; the ac current capability should be about 0.5 a. providing a reference voltage of 0.5 v, 1- sensing resistors are needed. in slow decay mode, the resistors? power rating is approximately p r ? i rms 2 r sense d ? 0.25 w. a 1 - 0.25 w - 1% resistor is used. the charge pump uses recommended components (1n4148 diodes, ceramic capacitors and a 100 resistor to reduce emi). r = 18 k , c = 1.2 nf are connected to the rc pins, obtaining t off ? 16 s. a 5.6 nf capacitor has been placed on the en pin, and the pin is driven by the c through a 100-k resistor. with these values, if there is a short-circuit between two out pins or an out pin and gnd, the power dmos?s turn off after approximately 1 s, and t disable ? 240 s. table 2. application data application data value rotation speed 300 rpm (f ck = 1 khz) winding peak current 1 a maximum ripple 50 ma supply voltage 24 v 5% sequence wave mode table 3. motor data motor data value winding resistance 6.6 winding inductance 7.9 mh step angle 1.8/step maximum bemf at 300 rpm 15 v
application example AN2839 30/40 doc id 15104 rev 1 figure 34. application example with wave drive selected, the dissipating power is about 0.8 w. if the ambient temperature is lower than 50 c, with a 4 cm 2 copper area on the pcb and an so24 package, the estimated junction temperature is about 94 c. using more copper area or a powerdip package will reduce the junction temperature. am01717v1
AN2839 demonstration board doc id 15104 rev 1 31/40 appendix a demonstration board a.1 practispin tm practispin tm is an evaluation and demonstration system that can be used with the powerspin tm family (l62xx) of devices. a graphical user interface (gui) program (shown in figure 35 ) runs on an ibm pc under windows and communicates with a common st7-based interface board ( figure 36 on page 32 ) through the rs-232 serial port. the st7 interface board connects to a device-specifi c demonstration board (target board) via a standard 34-pin ribbon cable interface. depending on the target device, the practispin tm can drive a stepper motor, 1 or 2 dc motors or a brushless dc (bldc) motor, operating significant parameters such as speed, current, voltage, direction, acceleration and deceleration rates from a user-friendly graphic interface, and programming a sequence of movements. the software can also evaluate the power dissipated by the selected device and, for a given package and dissipating copper area on th e pcb, estimate the device's junction temperature. figure 35. practispin tm pc software am0171 8 v1
demonstration board AN2839 32/40 doc id 15104 rev 1 figure 36. practispin tm st7 demonstration board a.2 l6228n evaluation with eval6208n to easily evaluate the device in powerdip pa ckages, it is possible to use the eval6208n, replacing the device directly on the available socket. we recommend changing the sense resistor values to manage lower load currents according to the device?s specifications. the eval6208n?s electrical schematic is shown in figure 37 on page 33 . for more information, refer to an1451 "l6208 fully-integrated two-phase stepper motor driver". a.2.1 important notes jp1: should be closed in the int position for use with the practispin tm st7 board. c6: recommended change to 5.6 nf for safe overcurrent protection. r8: recommended change to 100 k for safe overcurrent protection. r9: recommended change to 100 k if en pin is driven from the cn5 connector (for example with practispin tm st7 board) for safe overcurrent protection. r20, r24: set the maximum current obtainable through practispin tm (see practispin tm documentation). r2: recommended change to adequate value (depending on supply voltage) to obtain 5 v across d3. !-v
AN2839 demonstration board doc id 15104 rev 1 33/40 figure 37. eval6208n electrical schematic !-v &/2&. ',$* +$/))8// &21752/ ',$* 5&$ 5(6(7 (1 5&$ &:&&: 5(6(7 (1 &:&&: &/2&. 95()$ 95()% &/2&. +$/))8// 95()% &21752/ 95()$ 9&&5() 3xoo8s 3xoo8s 3xoo8s 3xoo8s 3xoo8s 3xoo8s 3xoo8s *1' 5&$ 5&% 95()% 95()$ &/2&. ',$* 9 9 lqw h[w &: &: &: &: (1 &: &&: +$/) )8// 6/2: )$67 ,. ' ' & & 5 5 5 5 & & 6 6 5 5 5 5 &1 &1 & & &1 &1 5 5 5 5 5 5 & & 5 5 5 5 &1 &1 5 5 5 5 & & 5 5 5 5 5 5 6(16($ 5&$ &/2&. 5&% &21752/ 95() $ &:&&: 95()% 6(16(% (1 5(6(7 +$/))8// 287$ *1' *1' 287% 9%227 287% 96% *1' *1' 96$ 287$ 9&3 8 8 5 5 ' ' 5 5 5 5 5 5 & & & & -3 -3 ' ' 5 5 & & &1 &1 5 5 & & 5 5 &1 &1 & & 5 5 5 5
demonstration board AN2839 34/40 doc id 15104 rev 1 a.3 eval6228qr a demonstration board has been designed to help in the evaluation of the device in qfn packages. the board implements a typical application that can be used as a reference design to drive a two-phase bipolar stepper motor with currents up to 1 a dc. thanks to the l6228q?s small footprint (qfn 5 x 5 mm 32 leads), the pcb is very compact (27 x 32 mm). figure 42 on page 37 shows the electrical schematic of the board. ta b l e 4 reports the parts list. figure 38. eval6228qr a step clock input is used to apply a clock signal that determines the progress of the internal state machine. it can be reset to its in itial state by pulling down the reset line. to perform the pwm current control, an analog reference voltage should be provided to each of the driver?s channels. a fixed reference voltage can be easily obtained through a table 4. eval6228qr parts list part reference part value part description c1 220 nf/25 v capacitor c2 220 nf/63 v capacitor c3 100 f/63 v capacitor c4 10 nf/25 v capacitor c5 5.6 nf capacitor c6, c6 820 pf capacitor c8, c9 220 nf capacitor d1 bat46sw diodes r1, r2, r3, r4, r5, r8 100 k 5% 0.25 w resistor r6, r7 100k 1% 0.25 w resistor r9, r10 0.4 1 w resistor r11, r13 20 k 1% 0.25 w resistor r12, r14 2 k 1% 0.25 w resistor u1 l6228q stepper motor driver in vfqfpn5x5 !-v
AN2839 demonstration board doc id 15104 rev 1 35/40 resistive divider from an external voltage rail and gnd (possibly the one supplying the c or the rest of the application). otherwise, a very simple way to obtain a variab le voltage without using a dac is to low-pass filter a pwm output of a c . the input lines cw/ccw, control, half/full, en and reset are connected to ground through a pull-down resistor which sets as default the low logic level on these lines. an external signal can be applied to change each input status. d1, c1 and c4 make up a charge-pump circuit, which generates the supply voltage for the high-side integrated mosfets. due to voltage and current switching at relatively high frequencies, these components are connected together through short paths in order to minimize induced noise on other circuitries. r1 and c5 are used by the overcurrent protection?s integrated circuitry (the disable time t disable is about 200 s and delay time t delay about 1 s with the values in ta bl e 4 ). r6, c6 and r7, c7 are used to set the off time toff of the two pwm channels at about 50 s. the off time should be adjusted according to the motor?s electrical characteristics and supply voltage by changing th e r6, c6 and r7, c7 values. r11, r12, c8 and r13, r14, c9 are low-pass filters used to provide an external reference voltage through a pwm output of a c. figure 39 and figure 41 show the components? placement and the two layers of the eval6228qr reference design board. a gnd area has been used to improve the ic?s power dissipation. figure 39. eval6228qr component placement !-v
demonstration board AN2839 36/40 doc id 15104 rev 1 figure 40. eval6228qr top layer figure 41. eval6228qr bottom layer !-v !-v
AN2839 demonstration board doc id 15104 rev 1 37/40 figure 42. eval6228qr electrical schematic !-v 96 3*1' 6*1' (1 5(6(7 +$/))8// &21752/ &:&& : &/2&. ',$* 287$ 287$ 287% 287% 5()% 5()$ /4 5 5 & & 5 5 5 5 & & 5 5 & & & & 5 5 5 5 & & & & 5 5 *1' &/2&. *1' 6(16($ 9%227 &21752/ 96% &:&& : 5&$ 96$ 9&3 95() $ (1 5&% +$/))8// 5(6(7 95()% 287$ 6(16(% 287% 287$ 287% 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 8 / 4 9)4)31[ 8 / 4 9)4)31[ 5 5 5 5 5 5 5 5 5 5 & & & & ' %dw6 : ' %dw6 : 5 5 & & 5 5
references AN2839 38/40 doc id 15104 rev 1 references 1. "a new fully integrated stepper motor driver ic", proceedings of pcim 2001, september 2001, intertech communication. 2. "stepper motor driving" (an235). 3. "controlling voltage transients in fu ll bridge driver applications" (an280). 4. "stepper motor drive considerations, common problems and solutions" (an460). 5. "microstepping stepper motor drive using peak detecting curren t control" (an1495). 6. "a new high power ic surface mount package family" (an668).
AN2839 revision history doc id 15104 rev 1 39/40 revision history table 5. document revision history date revision changes 22-sep-2009 1 initial release.
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